HamNet Packet Radio Tutorial - Part Two --------------------------------------- by Scott Loftesness W3VS CompuServe 76703,407 . . We'll continue our tutorial on packet radio by reviewing in more detail the hardware and software implemented on the Tucson Amateur Packet Radio (TAPR) Terminal Node Controller (TNC). . . The TAPR TNC is a self-contained, microprocessor-based device intended to act as an intelligent interface between a user's ASCII communcations system (terminal or computer) and radio-based packet communications. . . A 6809 microprocessor acts as the system CPU in the TAPR TNC. The 6809 is readily available and widely accepted for application in dedicated function controllers as well as general purpose low-end computers. It executes the software stored in the system's EPROM's. . . The 6809 has an internal 2-phase clock generator and provides control, address, and data bus input/output for family peripheral devices. It has capabilities for position-independent code and is designed to support multiple stacks, making it very efficient for executing block structured high level languages such as Pascal and Forth. Information on the 6809 architecture is available in Motorola, Hitachi, and AMI literature - and in several books which are widely available in the computer sections of most bookstores. . . The serial port is designed to provide a full-duplex RS-232-C interface for the user's terminal or personal computer. Full baud rate selection from 50 baud to 19.2 kilobaud is supported by the port. EIA RS-232-C levels and transition rates are implemented as well. The serial port is controlled by a 6551 LSI UART which contains an internal, software-controlled baud-rate generator. The transmitter and receiver are double-buffered and capable of interrupt-driven operation. The 6551 supports hardware flow control - allowing the terminal or computer to pace input and output from the TNC. 1488 and 1489A devices are used to translate the TTL levels from the 6551 to RS-232-C levels for the port itself. . . A parallel port is also included on the TAPR board. Although not used for terminal support in the initial releases of the supporting software, it is used for certain status indications. A 6820 is used to provide two 8-bit TTL-level handshaking ports. . . The system port interfaces to other devices on the TNC itself. These include a non-volatile RAM chip used to store certain of the system parameters across power-downs, DIP switches used for certain reset options, the HDLC controller chip, and an indicator driver interface for a variety of LED-monitored system functions. Implemented using a 6522, the system port also includes timing functions used for HDLC baud rate generation, software timing functions, the CW identification, and on-board calibration of the modem frequencies. The 6522 is a very powerful LSI chip which incorporates a pair of 8-bit programmable I/O ports, four control lines (for handshaking), two 16-bit programmable timers/counters, and an 8-bit shift register. The non-volatile RAM is used to store system parameters that are not normally changed such as call sign, terminal attributes, and timing parameters, but which remain user alterable. This allows configuration changes for a given session only, or on a "permanent" basis. The system port also handles the interface to the radio push-to-talk circuitry. . . A Western Digital WD1933B HDLC controller is used to implement the HDLC standard bit oriented protocol including CRC check sum and zero bit insertion. The HDLC controller interfaces to an on-board 1200 baud modem providing phase-coherent AFSK modulation (with Bell 202 compatibility) using the EXAR 2206/2211 chips. Also included is the necessary impedance matching circuitry for interface to most popular amateur radio equipment. A 14-second hardware "watchdog" timer is inserted in series with the transmitter push-to-talk line to prevent accidental RF channel lockout which might be caused by a software error. . . A unique feature of the TNC is the capability for on-board calibration of the modem tone frequencies. This is accomplished using jumpers which allow for the modem to be disconnected from the HDLC chip. . . The on-board memory bank consists of six JEDEC-standard 28-pin "byte-wide" sockets. Three of these sockets are mapped for 2K static RAM's. The other three sockets are mapped as 8K EPROM or static RAM sites. The configuration supports 2716, 2732 and 2764-type EPROM's. A custom memory map PROM is included which provides the address decode for the ROM and RAM chips. . . Also included on the TAPR TNC board is a user wire-wrap area - primarily to allow custom interfaces to be developed to support unusual radio interface requirements. Power busses are included in the area so that active devices may be added directly onto the TNC board itself as may be required by the user. . . This completes the hardware description of the TAPR TNC. As you can see, it's a very complete design using the latest in LSI chip technology.